Connect Chip

  Micrograph of the Chip Copyright: RWTH IAS
27/11/2019

After the regular waiting time, the Connect Chip is back from the fab. First lab tests show good performance.

  XY graph on an oscilloscope showing the IAS logo Copyright: RWTH IAS

Right after delivery the chip was prepared for measurement. First an implemented easteregg was tested, where the IQ-DAC outputs on an XY plot of an oscilloscope show the IAS logo. But also further measurements of the PAs and other circuit blocks show very promising results.