Digitale Kalibriertechnik für PLL-basierte Modulatoren mit Signalvorverzerrung

Sappok, Sören; Heinen, Stefan (Thesis advisor)

Aachen / Publikationsserver der RWTH Aachen University (2008) [Dissertation / PhD Thesis]

Page(s): 145 S. : graph. Darst.

Abstract

The increasing demand of mobile applications of radio with low power demand led to the concept of the frequency modulation with constant envelopes. Those, with the production of integrated circuits arising costs depend on the used technology and the necessary chip area. Therefore the selection of the modulator must be met regarding these criteria. Today, almost all integrated circuits for applications of radio below 6 GHz are manufactured in complementary transistor logic. For highest integration and component density the structural widths of CMOS circuits until today are shrinked to under 100 Nm. The use of small technology structures is favourable in the reference to size and current consumption, but the fluctuations in the production process constantly increase. Thereby the actual sizes of the elements of the desired deviate. For capacities and resistances is to be counted on variations of 30%. It is indispensable for the adherence to the respective radio specification that determines parameters precisely be adjusted can. In order to compensate the process variations is it necessarily to calibrate the circuit after the production. Naturally in principle the possibility exists to adjust the fluctuations by an external measurement and a following trim. This requires the measurement of each individual chip and is possible only in a defined operating condition (temperature, etc.). In order to minimize costs is it more meaningfully the calibration on the chip to be integrated. For this in past beginnings a separate circuit part was planned, which detects and compensates the fluctuations. A calibration cycle can be periodically implemented uniquely in principle, when each switching on, or. A goal of the available work was the development of a calibration concept that digitally detects the fluctuations of the loop gain of a phase rule loop and places behind automatically in accordance with defaults. Against this concept the demand was made to detect the process variations digitally. The additionally needed chip area, and thus the arising costs, should be reduced to a minimum. This objective presupposes an approach, which does not only supplement an existing concept, but fundamental modulation architectures on these criteria examines. As high performance the twopoint-Delta-Sigma- and the Predistortionmodulation pointed out. In both cases modulation is used, in order to modulate the data signals. The Predistortion points a significant advantage out in relation to the variant of point of two. The path needed for the high-pass modulation must be implemented always similarly. Thus the task of a calibration is the adjustment of the similar to the digital data path. This draws itself from as implementation intensive. Therefore the Predistortion-PLL can be selected as suitable architecture. Due to the function mode of the modulator complete, send-site signal processing must be regarded from digital transmit data to the high frequency, similar output signal. For a mathematical view the linear Model of the rule loop is used. A detailed investigation of the individual components of the PLL is implemented in this work. An analytic investigation of the intoxication processes was examined in the simulation environment MatLab and optimized for the treatment by Fractional N PLLs. Thus, compared with conventional estimations, fast and precise Noisesimulationen of the system could be accomplished. The essential point of this work is the simulation of the output phase of the voltage-controlled oscillator. This reinforcement, and/or slope varies strongly by the process-conditioned fluctuation of the capacities and inductances of the VCO. The challenge for the solution of this problem lay now in Substantial one in two nuclear aspects. On the one hand the variation had to be quantitatively seized. Further this value had to be impressed as correcting variable into the controlled system. In both points an optimal solution could be found. For the detection of the output phase two suitable procedures could be found and/or developed, which make a digital collection for the momentary phase possible. This new beginning is based on the synchronous subsampling of an asynchronous high frequency signal. The fact, a digital value of the phase curve too received makes a simple adjustment for the loop gain possible by the use of a switchable power source. This procedure became the developed calibration technology to the radio system DECT adapted. For this the rule loop was laid out regarding fast settling time when simultaneous adherence to the spectral requirements. In the context of this work additionally a procedure was developed, which makes a systematic draft possible of the loop filter on the basis the demanded specifications. The results show that the technology presented here can undercut the demanded accuracy of the loop gain of +-1%. In principle it is possible for the examined DECT system to detect the reinforcement up to 0.0372%. Such a precise attitude is not necessary however. In order to keep the expenditure to the implementation of the calibration circuit as small as possible, the system was laid out, in order to adjust variations of approx. +-0,5%. The high frequency specifications could be thus completely kept. In summary it can be held that the results make a significant reduction of the necessary test procedures for highly integrated circuits for this work possible. A substantial step could be denied by this development for the economical production of integrated transmission concepts. The presented calibration technology points further a potential to the advancement into the direction of fully digital transmission concepts.

Identifier

  • URN: urn:nbn:de:hbz:82-opus-25003
  • REPORT NUMBER: RWTH-CONV-112901