Systemsimulationen zur funktionalen Verifikation von HF- und Mixed-Signal-Schaltungen
Joeres, Stefan; Heinen, Stefan (Thesis advisor)
Aachen / Publikationsserver der RWTH Aachen University (2008) [Dissertation / PhD Thesis]
Page(s): XII, 174 S. : graph. Darst.
With integrated Circuits getting more and more complex, the "human factor" is the biggest uncontrollable source of errors in the design process, leading to several design iterations. The resulting delays in time to market and additional costs for process and human resources are the cause of a high financial loss in semiconductor industry. To adequately detect the errors during the design process (misinterpretation of specifications, routing- and design errors, version differences,...), this work develops a method, to enable functional verification of RF- and mixed-signal-systems. Based on actual circuit examples, corresponding methods are presented and optimized for speed and performance aspects. To speed up the necessary transient simulations, equivalent models of the circuits are developed in Verilog-AMS. These models realize the RF specifications with highest accuracy, under consideration of the tradeoff between design complexity and simulation speed. Pin compatibility is a main issue here. Traditional modeling methods are especially in the rf and mixed-signal part not sufficient to allow for functional verification of SoCs, mainly due to the effect of high frequency signals, leading to small time steps during simulation. This work focuses therefore on the mathematical backgrounds, to realize transient models based on rf specifications, which are usually described in frequency domain. Under careful consideration of the possibilities of the available simulators and modeling languages, an implementation of a virtual system example is realized, as well as implementations of commercial available circuits from industry partners. A special focus is laid on modeling using event driven simulators and techniques, which allow for more efficient simulation with analog accuracy. This enables to separate the RF signals from the larger baseband part of the chip, resulting in the possibility of system simulations for the whole SoC. Compared to other approaches, the simulation speed for phase locked loops has been enhanced by a factor of 55. For full chip simulations a speedup of 7900 compared to traditional methods was achieved, only topped by a speedup of 10e7 by baseband modeling methods. This work was supported by close contact to international semi conductor companies, and, besides the research area, takes special care of establishing the developed design flow in industrial appliances.
- URN: urn:nbn:de:hbz:82-opus-25508
- REPORT NUMBER: RWTH-CONV-113094