Nanoscale SoC-kompatibler FM-Radio Transmitter auf Basis einer vollständig digitalen PLL

Neyer, Andreas August (Author); Heinen, Stefan (Thesis advisor)

Aachen / Publikationsserver der RWTH Aachen University (2010) [Dissertation / PhD Thesis]

Page(s): XVIII, 184 S. : Ill., graph. Darst.


Almost every household is equipped with at least one FM radio receiver. However, music is now increasingly available in digital form as an MP3 file, e. g. on a phone as a mobile media player. As a result, an interface between the mobile phone as music player and the classic radio as a playback device is usually missing. The aim of this study is the implementation of an FM radio transmitter for "System on a Chip" (SoC) integration to close this gap. The co-integration of an FM radio transmitter with additional circuitry and signal processors allows playback of stored digital media on existing analog radio receivers. Thus, for example, when integrated in a radio chip for mobile phones, the mobile phone can function as an FM radio station. The support of the RDS standards allows it to transmit additional information such as the title. The implementation of the FM radio station is based on a modern all-digital phase locked loop (PLL), which is competitive only by the progress of CMOS integration to traditional mixed-signal PLLs. The continuous reduction of the minimum feature size of integrated circuits has reached 45nm and the next technology node (32nm) is close to introduction. For cost reduction, a joint production reduction of analog and digital parts on a chip, "System on a Chip", is aimed for. This development brings a number of advantages for the design of integrated digital circuits, because development is very much driven by digital circuit design and manufacturing processes are optimized for these. The maximum clock rate and thus computing power increase, while the supply voltage, the space requirements and power consumption are reduced. Integrated analog circuit design, however, does not benefited from this development. This progress means new challenges for integrated analog circuit design. For example, the reduction of minimum feature size brings little or no space advantage for analog circuits, as they scale poorly with the minimum feature size. Therefore, it is desirable to replaced analog circuit components by digital ones in order to benefit from future process development. To motivate the digital PLL, the differences in the structure and the benefits of the approach compared to a conventional PLL are presented. The main advantage of the presented approach is the lack of almost all analog components. Thus, the digital PLL is particularly suitable for the desired integration with other circuit blocks, and for production in processes, which are optimized for digital circuits. By using a hardware description language for circuit synthesis rapid adaptability and transfer in other manufacturing processes is guaranteed. For the realization of a test chip a common 90nm CMOS technology was used in this work. With regard to the intended use in mobile devices a low power consumption is an essential design aspect. For further cost reduction no external components are used, specifically external coils, which are usually used in this frequency range, are not required. In addition to the "full-custom" design of analog and mixed-signal components (simulation, and layout) the work includes the high level description and synthesis of the digital part of the PLL, and a description of the simulation methodology and modeling. To verify the simulation results a test chip was manufactured and measured. The simulation and measurement results are then compared and evaluated. In respect to the future development of production processes and SoC integration is expected that the underlying concept of an all-digital PLL will gain importance. It benefits not only by area reduction of the digital section, but also by the higher frequency and phase resolution of the oscillator and the phase detector.


  • URN: urn:nbn:de:hbz:82-opus-32162