Design and implementation of a broadband RF-DAC transmitter for wireless communications

Zimmermann, Niklas; Heinen, Stefan (Thesis advisor)

M√ľnchen / Hut (2011) [Dissertation / PhD Thesis]

Page(s): XX, 151 S. : Ill., graph. Darst.

Abstract

Next generation mobile communication standards have high demands on the radio-frequency (RF) frontend performance of mobile devices. New OFDM based mobile standards like 3GPP LTE, WiMax, or WLAN require a high signal bandwidth, high dynamic range as well as a high reconfigurability. Moreover, for each communication standard and frequency band an own RF transceiver is needed for state-of-the-art handhelds. To reduce the needed number of transceivers for devices like smartphones,a reconfigurable RF-frontend is needed, in order to save chip and PCB area and hence cost. Longterm goal is the so-called "Software Defined Radio" (SDR). In the framework of this thesis, a reconfigurable, mostly digital transmitter was developed, which utilizes a so-called RF-DAC. The RF-DAC unites digital-to-analog converter (DAC) and upconversion mixer in a single building block. Thereby, it is possible to convert digital signals directly to RF modulated signals. The usage of an RF-DAC allows the elimination of the all analog baseband signal blocks, like filters and baseband amplifiers. Instead, they are replaced by digital, programmable circuits. Furthermore, all transistors in the RF-DAC operate as switches. The requirements on the "analog" performance of the transistors is low. Hence, RF-DAC based transmitters are especially suited for the implementation in "nanoscale" CMOS technologies with feature sizes of 65nm and below. These CMOS technologies enable high-performance digital circuits as well as a low-cost mass production. In this thesis, first a system concept for an RF-DAC based transmitter, which supports high data rates, is discussed. The RF-DAC architecture has the drawback, that it is not feasible to implement a reconstruction filter within the monolithic connection of DAC and mixer. As a consequence, the RF-DAC emits unwanted signal replica at multiples of the DAC sampling rate. Therefore, special emphasis has been laid the analysis of techniques to reduce these unwanted emissions. Furthermore, a circuit implementation of an RF-DAC based I/Q vector modulator has been conducted and is thoroughly discussed. The RF-DAC has a resolution of 9bit and a maximum sampling rate of 850 MHz. A novel RF-DAC implementation allows especially high output power levels and at the same time a low power consumption at low signal amplitudes. Measurements of the fabricated chip prove the capability of the transmitter. A maximum output power of +16dBm is one decade higher than the power levels of comparable architectures. The power consumption drops from 280mW for a full-scale sinusoidal signal with +14dBm output power to 47mW when reducing the amplitude by 48 dB. This shows the effectiveness of the above mentioned measures to reduce power consumption at low signal amplitudes. In addition to the amplitude resolution of 8bit, the output power can be scaled in a range of more than 80 dB by varying the biasing currents. The RF-DAC transmitter is able to process 20 MHz wide 64QAM OFDM WLAN signals and fulfills the spectral mask the IEEE 802.11n standard.

Identifier

  • ISBN: 978-3-8439-0042-3
  • URN: urn:nbn:de:hbz:82-opus-37561
  • REPORT NUMBER: RWTH-CONV-114229