A feedback interference cancellation technique for mitigation of blockers in wireless receivers

Werth, Tobias Daniel; Heinen, Stefan (Thesis advisor)

Aachen / Hut (2011, 2012) [Dissertation / PhD Thesis]

Page(s): XVI, 172 S. : Ill., graph. Darst.


In recent years, availability and speed of mobile communication systems have considerably increased enabling accesss to information anywhere and anytime. This has been facilitated by evolution of mobile communication standards from voice-centric 2nd generation standards like GSM towards data-centric standards of the 3rd and 4th generation like UMTS and LTE. As the 2G net infrastructure is widely installed in the field and hence providing very good coverage successive standards usually do not replace but complement legacy standards by additional functionality. Consequently, handsets must support an increasing number of standards and frequency bands. Despite increasing complexity cost and form factor of the handset must be preserved. In the cellular market, this is usually achieved by taking advantage of high-integration in cost-effective CMOS technologies and economonies of scale. Still, this trend is hindered by external components which are not amenable to CMOS integration. In particular, the number of external passive surface acoustic wave (SAW) filters rises with the number of frequency bands and standards. These filters are required to reduce out-of-band interferers, need large area and contribute to overall handset cost. Therefore, this work aims at replacing external SAW filters by an active filter which can be integrated with the receiver in CMOS thus leading to overall cost and printed circuit board area reduction. This work investigates a concept which uses a high-frequency control loop to detect and suppress interferers. First, a system model is derived to obtain criteria for filter selectivity and control loop stability. A first implementation in a 65-nm CMOS technology demonstrates feasibility. Thus, a filter selectivity of 10.5 dB is obtained at a gain of 25 dB and a noise figure of 7 dB. Moreover, gain degradation at a -15 dBm interferer is reduced by more than 9 dB. Subsequently, the concept is extended to a GSM direct-conversion receiver from 1.8 - 2 GHz. Circuit specifications for a GSM receiver with SAW filter are derived and contrasted to a GSM receiver with integrated interference cancellation loop. The integrated interference cancellation loop provides lower selectivity and requires lower local oscillator phase noise than the SAW filter implementation. Using the specifications a direct-conversion receiver with integrated interference cancellation loop is implemented in a 90-nm CMOS technology. As the interference cancellation loop does not linearize the input low noise amplifier (LNA) suitable topologies allowing for an input compression point of 0 dBm are investigated. The capacitive cross-coupled common-gate LNA is identified as a good compromise between noise and linearity and implemented in a 90-nm CMOS technology. The test chip has a gain 20 dB, a noise figure between 3.3 and 4.2 dB and input compression points between -3 and 0 dBm. The complete receiver has a noise figure of 3.3 dB with interference cancellation and 6 dB with interference cancellation. The input compression points are improved by 7 to 15 dB depending on the interferer offset frequency while the noise figure rises above 20 dB at high interferer power levels. Current consumption of the receiver (24 mA) and the interference cancellation loop (26 mA) have been considerably reduced in comparison to the first test chip implementation. The results at hand promise that a GSM-compliant implementation can be achieved.


  • ISBN: 978-3-8439-0343-1
  • URN: urn:nbn:de:hbz:82-opus-39829