Design of Low Power Reconfigurable Continuous Time Quadrature Bandpass $\Delta$ $\Sigma$ ADCs for Multi-Standard SoC

Atac, Aytac; Heinen, Stefan (Thesis advisor); Oehm, J├╝rgen (Thesis advisor)

Aachen (2016) [Dissertation / PhD Thesis]

Page(s): 1 Online-Ressource (xviii, 186 Seiten) : Illustrationen, Diagramme


Scaling of CMOS technologies has enabled the evolution of mobile multimedia communication for more than two decades. Combining analog, digital and mixed signal systems, System-on-Chip (SoC) solutions are commonly implemented in mobile electronics due to their high energy efficiencies. Furthermore, multiple systems having dedicated Analog-to-Digital Converters (ADC) are implemented within the same SoC. However, additional ADCs require more integrated chip (IC) area, battery power and advanced packaging technologies. Within the frame of this work, a reconfigurable ADC is developed that offers a single and flexible solution for multi-standard SoCs. Due to their power saving architecture and flexibility in their sub-circuits, the focus of this work is selected as quadrature bandpass continuous time (CT) ADC. The effects of converter resolution, sampling frequency and gain-bandwidth product on the total power consumption are analyzed. It is presented that a true reconfigurable ADC requires a scalable power budget as well as bandwidth, intermediate frequency and resolution. Furthermore, as a part of this work, a design and an automatic test method for reconfigurable ADCs is developed and implemented. The loop filter of the CT ADC constitutes an important part of the overall power consumption. Within the thesis, it is shown that gain-bandwidth products of the opamps forming the loop filter are decisive for the power budget and the stability of the loop and the requirements are different for each filter stage. In order to increase the converter efficiency, a variable gain-bandwidth opamp is designed achieving gain-bandwidth scaling from 50 MHz to 2 GHz and power scaling factor of 6. This opamp is implemented optimally for each stage of the filter. The second energy efficiency improvement is enabled via a scalable sampling clock frequency. To avoid any off-chip solutions, an on-chip DLL based clock multiplier circuit is developed as a part of this work that can multiply the clock frequency with any factor between 2 and 6 while consuming 500 A. Power and clock scaling are demonstrated with a chip design that achieves 0,5-1-1,5 MHz bandwidths and 78,4-65,2-56,4 dB dynamic ranges respectively. The ADC is implemented as a part of a multi-mode low power transceiver.To improve reconfiguration capability further, for the first time with this work, bit scaling using a tracking concept for CT ADCs is proposed and implemented. The tracking quantizer achieves multi-bit conversion using a single comparator only. The digital tracking algorithm is implemented that enables switching from single-bit to multi-bit using the same architecture. Eliminating power hungry comparators, a reconfigurable ADC is demonstrated which reaches a very high FOM of 0.019pJ/conv.


  • URN: urn:nbn:de:hbz:82-rwth-2016-088858
  • REPORT NUMBER: RWTH-2016-08885