Low power RF signal processing for internet of things applications
Aachen (2016, 2017) [Dissertation / PhD Thesis]
Page(s): 1 Online-Ressource (xxii, 150 Seiten) : Illustrationen, Diagramme
In this work, low effort architectures for Internet of Things (IoT) applications are proposed to support multiple short-range wireless standards on single die. Appropriate solutions for low power RF transceiver are provided, which emphasize the high-efficient, low-cost, low-power performance but with satisfactory data rate. By comparing the characteristic trade-offs of the various architectures, analyzing the typical transceiver non-ideality factors and discuss the specifications and requirements of typical short distance standards, the PLL based two-point modulation transmitter and low-IF receiver architectures are selected.In the transmitter design, a current-reuse VCO technique in the frequency synthesizer is presented to significantly reduce the power consumption with excellent phase noise performance. Subsequently a digital architecture for ΣΔ quantizer and noise cancellation is proposed in the PLL modulation loop, which can dramatically reduce the hardware complexity without degrading the Synthesizer performance. To enhance the two-point modulation bandwidth, an adaptive calibration technique for phase noise cancellation based on the modified classical loop filter structure is proposed, where an additional port from the loop filter is used as the reference for the Least Mean Square (LMS) algorithm to avoid DC offset. The gain mismatch between signal path and noise cancellation path is detected and calibrated outside of the PLL loop without introducing any additional spurs into the system. Comparing to the previous works, the proposed technique provides a straightforward solution for wideband PLL designs, and the quantization noise is successfully eliminated with smaller area and lower power consumption.In the receiver design, the proposed low-power low-effort digital demodulator architecture for low-IF receivers can compensate I/Q mismatch due to the impairment within the frontend, and thus it improves the robustness against interference presented at the image frequency. And the group delay is compensated with a digital IIR based equalizer, which improves the BER performance significantly compared to the original case. In the clock data recovery block, the typical synchronization problems including symbol timing recovery and carrier frequency offset calibration are solved based on a simplified Data-Aided (DA) scheme. The ΣΔ NCO provides wide range IF signals with high resolution and SNR. A Viterbi decoder which uses multi-order differential discriminators provides a robust decoding performance. Hence, it can be demonstrated that the proposed multi-standard receiver architecture not only greatly enhances the performance with wide range data rates and IF frequencies, but also provides an easy, feasible and flexible solution for the fully integrated implementation.